Semiconductor integrated circuit (IC) devices utilize a pair of voltage levels—one higher and one lower, in the performance of their data processing operations. Toggling between the voltage levels serves as a binary signal—“1” at the higher voltage level or “0” at the lower voltage level. The signal is “read” by transistors and propagated throughout the device. In response to these voltage changes, current flows across the power net of the device flowing to and through its multitude of transistors according to the logical design of the circuit. This current flow consumes electric power.
As demand for greater capacity and performance in an ever smaller size semiconductor package has increased, so too have transistor counts and IC chip densities. In an effort to reduce power consumption, engineers have been designing transistors to function on decreasing operating voltages. This creates situations in which a large amount of current is being used at relatively low voltage (currently about 1.0V) in very tightly configured integrated circuitry. To operate properly, this lower operating voltage requires a very tight tolerance, typically within 3% of its design value.
CMOS transistors typically draw most of their current as they change state, e.g. as the binary signal changes from a 0 to a 1, or vice-versa. These state changes occur just after the rising clock edge for synchronous circuits. Synchronous circuits comprise many components of ICs. Since all synchronous IC circuits are typically coordinated by the same internal clock, all of the transistors that draw power during switching do it at the same time, resulting in large current spikes on the power net of the IC.
As anyone skilled in the art of integrated circuit design is aware, sudden changes in current within a circuit results in inductive voltage transients. These voltage transients are felt by neighboring circuits within the device. Large current spikes can produce voltage transients which are outside the operating range tolerance and can lead to false signals and operational failures.
This situation, although recognized in earlier designs of solid state devices, was not so significant. But with the development of sub-micron dimensional circuit features, inductive effects on low-power consumption, densely-packed circuits are now governing the design of new chips.
Presently this transient voltage problem is addressed by placing the power supply as close as possible to the chip and/or using sense lines on the power supply to create a tight regulation at the load. Decoupling capacitors also help to reduce the voltage transients generated between the power supply and the load. While helpful, these design techniques cannot eliminate the voltage transients caused by large current changes and have no effect on the voltage transients caused by the inductance on the IC power net from the package pins to the silicon.
Multi-chip module packaging further exacerbates this problem. Processors, including DSP and microprocessors, routinely are designed for the ability to perform a variety of tasks simultaneously utilizing a plurality of different functional modules within the chip. As multi-tasking operations progress under the influence of the synchronizing chip clock, the incidence of simultaneous signal (current) changes and their attendant voltage transients increases. The present invention reduces the simultaneity of signal switching in a majority of these circuits, lower voltage (and thus lower power) devices could be employed with greater signaling reliability.
Large ICs typically comprise relatively independent functional modules which perform their operation before passing their output on to either another module or to another part in the device. Prior art discloses that when clock signals become delayed (skewed) between data transmitters and receivers, FIFO buffers may be utilized within latch control circuits to overcome the phase uncertainty (refer to U.S. Pat. No. 6,486,721 by Greenstreet).
Prior art also discloses that where clock signals become delayed to synchronous parts, on-chip clock delay circuits can be introduced to resynchronize the clock signal to such parts (refer to U.S. Pat. No. 6,621,882 by Denny).